1. Field of the Invention
The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a semiconductor memory device allows a reduction of test time for testing the semiconductor device.
Priority is claimed on Japanese Patent Application No. 2008-279746, filed Oct. 30, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, there has been used a parallel test that tests, at the same time, a plurality of semiconductor memory devices such as double data rate-random access memories, hereinafter referred to as a DDR-RAMS. The parallel test may be carried out as disclosed in Japanese Unexamined Patent Application, First Publication, No. JP-A-2008-181594. A tester gives the semiconductor memory device an input of a clock signal, which is lower in rate than a normal clock signal, in order to test data input/output functions of the semiconductor memory device and memory elements. The normal clock signal is a clock signal that is used in the general operation mode. In this parallel test, when a read or write command and a column address are input to the semiconductor memory device, the semiconductor memory device is operated to drive a test mode read signal in synchronization with the rising edge or the falling edge of the input clock signal. The test mode read signal can act as a column selection signal and can be used to select data output from a memory cell array.